The present invention generally relates to adders, and more particularly to an adder for adding binary numbers in an electronic calculator and the like.
The operation speed of an adder which adds two binary numbers can be increased effectively by reducing the propagation speed of a carry bit. Various proposals have been made to reduce the propagation time of the carry bit. FIG. 1 shows an example of a conventional 4-bit adder.
The 4-bit adder comprises a plurality of NAND gates 100.sub.0 through 100.sub.3, NOR gates 101.sub.0 through 101.sub.3 and 102.sub.0 through 102.sub.3, AND gates 103.sub.0 through 103.sub.3 and 104 through 117, exclusive-OR gates 118.sub.0 through 118.sub.3 and inverters 119 and 120. A circuit part 130 indicated by a phantom line corresponds to a circuit for quickly outputting a carry bit signal C.sub.3. A composite gate 131 made up of AND-NOR gates is inserted between a carry bit input terminal for receiving a carry bit signal C.sub.-1 and a carry bit output terminal for outputting a carry bit signal C.sub.3. The carry bit signal C.sub.-1 from a lower adder (not shown) is applied to the carry bit input terminal, and the carry bit signal C.sub.3 to a higher adder (not shown) is outputted from the carry bit output terminal.
In FIG. 1, A.sub.0 through A.sub.3 denote bits of a first binary value which is to be added to a second binary value, B.sub.0 through B.sub.3 denote bits of the second value and S.sub.0 through S.sub.3 denote bits of a binary sum of the first and second binary values.
FIG. 2 shows an example of a composite gate made up of a 2-input AND gate 140, a 3-input AND gate 141 and a 2-input NOR gate 142. Further, FIG. 3 shows the actual circuit construction of the composite gate shown in FIG. 2 constituted by n-channel metal oxide semiconductor (MOS) transistors Q1 through Q10. In FIGS. 2 and 3, a, b, c, d and e denote input signals of the composite gate and OUT denotes an output signal of the composite gate outputted from an output terminal.
As may be seen from FIG. 3, each of the signals a through e passes through two or three n-channel transistors. Hence, when the load capacitance of the output terminal is denoted by C and the resistance per n-channel transistor is denoted by R, the time constant of the signal propagation can be described by 2RC or 3RC. As a result, in the case of the adder shown in FIG. 1 and described above, the time constant of the carry bit propagation becomes 5RC, and a further reduction in the propagation time of the carry bit is prevented thereby.
Therefore, in this conventional adder, the propagation time of the carry bit is high because of the number of transistors used and the time constant of the bit propagation determined by the load capacitance of the output terminal and the resistances of the transistors.